Digital Design -DFT M/F

Job description

General information

Reference

2019-2045  

Job level

40 - Experienced

Position description

Posting title

Digital Design -DFT M/F

Regular/Temporary

Regular

Job description

A DFT activity leader role. The incumbent will be responsible for leading few of the activities of advanced DFT/DFD/DFM (design for test/debug/manufacturability) techniques for developing innovative Driver Assistance System(ADAS) for futuristic cars from the stable of leading car manufacturers ( Eg-Daimler,-Benz, BMW, VOLVO) . The candidate selected will also be involved in all aspects of DFT including methodology development, vector development, manufacturing testing, and debug.

The job perimeter includes:

DFT architecture specification
DFT RTL coding and integration.
SCAN and LBIST insertion
High Speed interface DFT management
Memory BIST specification and insertion
Interaction with Front End, Back End &Test Engineers located at various sites (France, Italy and India)

Profile

Strong team work and communication and quick learning are key skills.
Good RTL (VHDL or Verilog or System Verilog) writing skills
SOC integration and RTL modification as per DFT requirement.
Good at DFT Spyglass checks.
Expert of DFT technique and tools (Scan, ATPG, JTAG, LBIST, DFT architecture)
Working Knowledge of MBIST architecture and tools (SMS, MMB).
Working Knowledge in scripting language (TCL, Perl, MASIS, ...)
Working Knowledge of High-Speed interface testing is a plus (i.e. LPDDR4, PCI, MIPI)
Expertise to use industry standard tools like Tetramax, Design Compiler, etc.
Expertise in RTL and Back Annotated Gate-level simulations and debug especially GLS for ATPG.
Working Knowledge of Boundary Scan Testing and testing of IPs viz ADC, FLASH , PMU in standalone mode.
Working knowledge of Latest technique viz. Lowpower ATPG, Analog Bist, Logic Bist would be appreciated and preferred.
Ownership of DFT STA constraints. PT2TMAX flow for ATPG STA is desirable.
Expert in ATPG coverage analysis to achieve StuckAt coverage more than 99% at SoC level.
Experience in follow-up of tool issues with EDA CAD vendors and successful closure of issues.

 

Position localisation

Job location

Asia-Pacific, India, Greater Noida

Candidate criteria

Education level required

5 - Master degree

Experience level required

6-10 years

Languages

English (3- Advanced)

Requester

Desired start date

15/09/2019