Location: Europe, Italy, Catania
Type of contract: Regular
Job open date: 12/02/2020
Company department: Digital Verification Engineer
STMicroelectronics is a leading semiconductor company, a world key player thanks to our 43,200 employees including 8,300 working in R&D.
ST’s products are found everywhere today. And together with our customers, we are enabling smarter driving, homes, factories, and cities, along with the next generation of mobile and Internet of Things devices. Everywhere microelectronics makes a positive contribution to people lives, ST is there.
In 2018, we were ranked by the Randstad Employer Brand Research Award among the 5 most attractive companies in France, for our values of excellence, our integrity and the respect of our employees.
Design Arch SR ENG II/PL
· Education Level Required - Laurea Desired Competencies are - Digital Strategy Verification, Digital Design & Simulation.The Other skills required are - Basic knowledge of UVM/C Digital Verification environment
- Or some experience in UVM/C based methodology, System Verilog & Assertions, shell scripting and ARM SoC verification
- Or strong interest in UVM Digital Verification at IP level or SOC level.
· 5 - Master degree
· Less than 2 years
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