Domaine : Technologies micro et nano
Contrat : CDD
Description du poste :
This job position is part of a research project entitled “Smart-IMC” for “Sparsity-driven image sensor with MAchine-learning Resource-lighT based on In-Memory Computing”. This project aims to design an image processing co-processor (ISP) implementing edge-AI algorithms to perform spatio-temporal inferences (e.g., gesture recognition) taking imager raw data as input. This development will take advantage of advanced Hardware/Algorithm co-optimization for Machine Learning routines, in particular thanks to the In-Memory Computing paradigm (IMC). This Ultra Low Power AI hardware accelerator will be designed to be fully compatible for a future co-integration with an imager via 3D-stack IC technology.
This ISP will use a convolutional network (CNN) topology parts as well as Gated Recurrent Units. The dedicated topology will benefit from algorithmic enablers for Dimension Reduction. The use of this kind of tools will further allow co-optimization with a relevant IMC integration. In terms of accuracy, the target objective will be to be as close as possible to the precision of state-of-the-art inference algorithms while exhibiting a massive reduction in terms of hardware.
The candidate will be responsible for digital and mixed-signal design tasks related to the integration of IMC full-custom computational building blocks. He will be in charge of the front-end design and verification tasks, working in close relationship with the team of experts in In-Memory Computing, near-sensor processing and embedded Machine Learning. In addition, his work will rely on algorithmic topology descriptions provided by other members of the project team in order to result in designing and manufacturing the ISP chip.
The candidate must have a good experience of CMOS digital IC design with a global overview of the different steps of circuit design & validation. Having already practiced this kind of development process up to chip fabrication will be an undeniable advantage. Moreover, unconventional computing elements will require specific skills in full-custom mixed-design (near transistor), for which experts in the field will yet mentor the candidate. A solid background regarding ultra-low power design issues will certainly be promoted. Finally, since the chip application use-cases are related to Machine Learning and embedded Computer Vision, a basic academic knowledge of Neural Networks will definitively be a plus.
Ph.D. in microelectronics digital & mixed-signal design or M.Sc. with a least 2 years work experience.
Curiosity / Initiative / Team Spirit
Ville : Grenoble